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Staff/Senior ASIC Design/Verification Engineer



Accounting and Finance --> Account Payable

Chicago, IL
 • 
ID: 214647-921
 • 
Full-Time/Regular

We are committed to finding the best talent for a wide range of disciplines in the exciting semiconductor market. Innovative, enthusiastic, and success-oriented people are encouraged to join our team.

Exar’s work environment is informal, yet focused on results and professional growth. All employees are given visibility, responsibility, and an opportunity to excel -- characteristics of Exar’s values: employee communication, employee recognition and employee development and training.a


Required Skills

Design:
  • Overall chip architecture, system architecture experience
  • Experience in RTL design using verilog/VHDL.
  • Synthesis using synopsys DC, STA using prime time, formal verification using formality
  • Functional and gate level simulation and debugging
  • Knowledge of T1,E1, T3,E3, sonnet/sdh, Ethernet, vcat, lcas, utopia, SPI-3, SPI-4, framing algorithms, PCI-express, SATA, embedded processor
Verification:
  • Experience writing testbench/model in verilog, system verilog
  • Understanding of VMM using system verilog
  • Functional and gate level simulation and debugging
  • Knowledge of T1,E1, T3,E3, sonnet/sdh, Ethernet, vcat, lcas, utopia, SPI-3, SPI-4, framing algorithms, PCI express, SATA, embedded processor

Required Experience

RTL and test bench coding using Verilog is required
Synthesis using Synopsis DC and STA using primetime a plus
Knowledge of T1/E1. T3/E3. Spmet/SDH, Ethernet protocols a plus
Knowlege of Xilinx/Altera FPGA implementation is a plus

6 - 10 Years Experience
BSEE required
MSEE desired


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